1. Field of Invention
The present invention relates to semiconductor manufacturing. More particularly, the invention relates to the generation of an organic plug for an IC structure.
2. Description of Related Art
In semiconductor integrated circuit (IC) fabrication, devices such as component transistors are formed on a semiconductor wafer substrate that is typically made of silicon. During the fabrication process, various materials are deposited on the different layers in order to build a desired IC. Typically, conductive layers may include patterned metallization lines, polysilicon transistor gates and the like which are insulated from one another with dielectric materials. The dielectric materials have been formed from silicon dioxide, SiO2, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitances.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant, k, of the material used to form the dielectric layers. As noted above, the dielectric layers in prior art integrated circuits have traditionally been formed of SiO2, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO2 may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
One particular material that is being used as a low-k dielectric is organosilicate glass (OSG). OSG is a low-k material that can be deposited either by spin-on or CVD methods. The typical OSG k value ranges from 2.6 to 2.8. Porous OSG (pOSG) can also be used for low-k applications. Typically, porous materials such as pOSG are applied using spin-on methods and with controlled evaporation of the solvent providing the desired pore structure.
Typically, low-k materials are incorporated into IC fabrication using a copper dual damascene process. A dual damascene structure employs an etching process that creates trenches for lines and holes for vias. The vias and trenches are then metallized to form the interconnect wiring. The two well-known dual damascene schemes are referred to as a via first sequence and a trench first sequence.
During the dual damascene process, the via should be protected from faceting and fence formation. To protect the via from these problems, an organic plug is used. The process of generating the organic plug should have little or no effect on an IC structure. Thus, for an IC structure having an OSG dielectric material, the generation of the organic plug should have little or no effect on the OSG layer.